思澈科技软件开发工具包  2.20
DSI Private Macros

Macros

#define IS_DSI_PLL_NDIV(NDIV)   ((10U <= (NDIV)) && ((NDIV) <= 125U))
 
#define IS_DSI_PLL_IDF(IDF)
 
#define IS_DSI_PLL_ODF(ODF)
 
#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane)   (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
 
#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes)   (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
 
#define IS_DSI_FLOW_CONTROL(FlowControl)   (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
 
#define IS_DSI_COLOR_CODING(ColorCoding)   ((ColorCoding) <= 5U)
 
#define IS_DSI_LOOSELY_PACKED(LooselyPacked)   (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
 
#define IS_DSI_DE_POLARITY(DataEnable)   (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
 
#define IS_DSI_VSYNC_POLARITY(VSYNC)   (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
 
#define IS_DSI_HSYNC_POLARITY(HSYNC)   (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
 
#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType)
 
#define IS_DSI_COLOR_MODE(ColorMode)   (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
 
#define IS_DSI_SHUT_DOWN(ShutDown)   (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
 
#define IS_DSI_LP_COMMAND(LPCommand)   (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
 
#define IS_DSI_LP_HFP(LPHFP)   (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
 
#define IS_DSI_LP_HBP(LPHBP)   (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
 
#define IS_DSI_LP_VACTIVE(LPVActive)   (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
 
#define IS_DSI_LP_VFP(LPVFP)   (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
 
#define IS_DSI_LP_VBP(LPVBP)   (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
 
#define IS_DSI_LP_VSYNC(LPVSYNC)   (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
 
#define IS_DSI_FBTAA(FrameBTAAcknowledge)   (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
 
#define IS_DSI_TE_SOURCE(TESource)   (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
 
#define IS_DSI_TE_POLARITY(TEPolarity)   (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
 
#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh)   (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
 
#define IS_DSI_VS_POLARITY(VSPolarity)   (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
 
#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest)   (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
 
#define IS_DSI_ACK_REQUEST(AcknowledgeRequest)   (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
 
#define IS_DSI_LP_GSW0P(LP_GSW0P)   (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
 
#define IS_DSI_LP_GSW1P(LP_GSW1P)   (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
 
#define IS_DSI_LP_GSW2P(LP_GSW2P)   (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
 
#define IS_DSI_LP_GSR0P(LP_GSR0P)   (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
 
#define IS_DSI_LP_GSR1P(LP_GSR1P)   (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
 
#define IS_DSI_LP_GSR2P(LP_GSR2P)   (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
 
#define IS_DSI_LP_GLW(LP_GLW)   (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
 
#define IS_DSI_LP_DSW0P(LP_DSW0P)   (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
 
#define IS_DSI_LP_DSW1P(LP_DSW1P)   (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
 
#define IS_DSI_LP_DSR0P(LP_DSR0P)   (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
 
#define IS_DSI_LP_DLW(LP_DLW)   (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
 
#define IS_DSI_LP_MRDP(LP_MRDP)   (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
 
#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE)
 
#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE)
 
#define IS_DSI_READ_PACKET_TYPE(MODE)
 
#define IS_DSI_COMMUNICATION_DELAY(CommDelay)   (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
 
#define IS_DSI_LANE_GROUP(Lane)   (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
 
#define IS_DSI_CUSTOM_LANE(CustomLane)   (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
 
#define IS_DSI_LANE(Lane)   (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
 
#define IS_DSI_PHY_TIMING(Timing)
 

Detailed Description

Macro Definition Documentation

◆ IS_DSI_LONG_WRITE_PACKET_TYPE

#define IS_DSI_LONG_WRITE_PACKET_TYPE (   MODE)
Value:
(((MODE) == DSI_DCS_LONG_PKT_WRITE) || \

◆ IS_DSI_PHY_TIMING

#define IS_DSI_PHY_TIMING (   Timing)
Value:
(((Timing) == DSI_TCLK_POST ) || \
((Timing) == DSI_TLPX_CLK ) || \
((Timing) == DSI_THS_EXIT ) || \
((Timing) == DSI_TLPX_DATA ) || \
((Timing) == DSI_THS_ZERO ) || \
((Timing) == DSI_THS_TRAIL ) || \
((Timing) == DSI_THS_PREPARE ) || \
((Timing) == DSI_TCLK_ZERO ) || \
((Timing) == DSI_TCLK_PREPARE))

◆ IS_DSI_PLL_IDF

#define IS_DSI_PLL_IDF (   IDF)
Value:
(((IDF) == DSI_PLL_IN_DIV1) || \
((IDF) == DSI_PLL_IN_DIV2) || \
((IDF) == DSI_PLL_IN_DIV3) || \
((IDF) == DSI_PLL_IN_DIV4) || \
((IDF) == DSI_PLL_IN_DIV5) || \
((IDF) == DSI_PLL_IN_DIV6) || \
((IDF) == DSI_PLL_IN_DIV7))

◆ IS_DSI_PLL_ODF

#define IS_DSI_PLL_ODF (   ODF)
Value:
(((ODF) == DSI_PLL_OUT_DIV1) || \
((ODF) == DSI_PLL_OUT_DIV2) || \
((ODF) == DSI_PLL_OUT_DIV4) || \
((ODF) == DSI_PLL_OUT_DIV8))

◆ IS_DSI_READ_PACKET_TYPE

#define IS_DSI_READ_PACKET_TYPE (   MODE)
Value:
(((MODE) == DSI_DCS_SHORT_PKT_READ) || \
((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \

◆ IS_DSI_SHORT_WRITE_PACKET_TYPE

#define IS_DSI_SHORT_WRITE_PACKET_TYPE (   MODE)
Value:
(((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \

◆ IS_DSI_VIDEO_MODE_TYPE

#define IS_DSI_VIDEO_MODE_TYPE (   VideoModeType)
Value:
(((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
((VideoModeType) == DSI_VID_MODE_BURST))
DSI_DCS_SHORT_PKT_WRITE_P0
#define DSI_DCS_SHORT_PKT_WRITE_P0
Definition: bf0_hal_dsi.h:806
DSI_DCS_SHORT_PKT_WRITE_P1
#define DSI_DCS_SHORT_PKT_WRITE_P1
Definition: bf0_hal_dsi.h:807
DSI_DCS_SHORT_PKT_READ
#define DSI_DCS_SHORT_PKT_READ
Definition: bf0_hal_dsi.h:827
DSI_GEN_SHORT_PKT_READ_P0
#define DSI_GEN_SHORT_PKT_READ_P0
Definition: bf0_hal_dsi.h:828
DSI_GEN_SHORT_PKT_WRITE_P1
#define DSI_GEN_SHORT_PKT_WRITE_P1
Definition: bf0_hal_dsi.h:809
DSI_GEN_SHORT_PKT_WRITE_P2
#define DSI_GEN_SHORT_PKT_WRITE_P2
Definition: bf0_hal_dsi.h:810
DSI_GEN_LONG_PKT_WRITE
#define DSI_GEN_LONG_PKT_WRITE
Definition: bf0_hal_dsi.h:819
DSI_GEN_SHORT_PKT_READ_P1
#define DSI_GEN_SHORT_PKT_READ_P1
Definition: bf0_hal_dsi.h:829
DSI_DCS_LONG_PKT_WRITE
#define DSI_DCS_LONG_PKT_WRITE
Definition: bf0_hal_dsi.h:818
DSI_GEN_SHORT_PKT_READ_P2
#define DSI_GEN_SHORT_PKT_READ_P2
Definition: bf0_hal_dsi.h:830
DSI_GEN_SHORT_PKT_WRITE_P0
#define DSI_GEN_SHORT_PKT_WRITE_P0
Definition: bf0_hal_dsi.h:808